Error (180000): fractional PLL is attempting to compensate for multiple LVDS clock tree(s), but it can compensate only for one LVDS clock tree (1 location affected) - Error (180000): fractional PLL is attempting to compensate for multiple LVDS clock tree(s), but it can compensate only for one LVDS clock tree (1 location affected) Description You will see this error message when attempting to use a side bank PLL to drive the ALTLVDS clocks on top or bottom banks in device families that only support the source synchronous SERDES on top and bottom banks. To drive top or bottom bank source synchronous SERDES channels, you must use a PLL on the same edge of the device as the LVDS I/O pins. Resolution This is a valid no-fit. The design failed in constraint propagation where user constraint fractional pll to FRACTIONALPLL_X0_Y46_N0 because this location doesn't drive LVDS. LVDS clock tree usually runs across the top and bottom edges. Custom Fields values: ['novalue'] Troubleshooting 2205791428 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix No plan to fix ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']