Why is the ready allowance smaller than the read latency of RX and TX Avalon® Streaming interfaces in the Arria® 10 Hard IP for PCI Express? - Why is the ready allowance smaller than the read latency of RX and TX Avalon® Streaming interfaces in the Arria® 10 Hard IP for PCI Express? Description Due to a problem in the Quartus® Prime Pro Edition Software version 21.2 and earlier, you may see the ready latency and the ready allowance of RX and TX Avalon® Streaming values of "3" and "0", which conflicts with the Avalon® Streaming specification that ready allowance should be equal or greater than ready latency. Resolution The ready allowance is in fact the same as the ready latency. You can ignore this display error. Custom Fields values: ['novalue'] Troubleshooting 1508876359 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']