(VHDL) I'm Receiving an Error When Trying to Access an Array - (VHDL) I'm Receiving an Error When Trying to Access an Array Hello All, I'm trying to output data inside an array to the 7-segment display on my DE1-SoC board. Here are my variables: display : out std_logic_vector (6 downto 0); type bigDisplay is array (0 to 4, 0 to 6) of bit; signal displayArray : bigDisplay; Here is the code: display <= displayArray (0, 6-0); This is the error I receive: Error (10381): VHDL Type Mismatch error at Final_Project.vhd(326): indexed name returns a value whose type does not match "std_logic_vector", the type of the target expression So, I'm guessing I need to convert my bit array to output to the std_logic_vector? How should I do this? Replies: Re: (VHDL) I'm Receiving an Error When Trying to Access an Array Alternatevely you might use: Type sevseg_t is std_logic_vector(6 downto 0); signal sevseg is array(0 to 4) of sevseg_t; And then you can directly use the returned value of the array. Also try using std_logic instead of bit asit helps to spot potential problems when simulating your design. Replies: Re: (VHDL) I'm Receiving an Error When Trying to Access an Array You can use the following to convert bit_vectors/ bit to std_logic_vector: Use IEEE.STD_LOGIC_1164 package's function To_StdLogicVector FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;