Why do I get the error message similar to below when compiling a PCI Express design in the Quartus® II software for Cyclone® V devices? - Why do I get the error message similar to below when compiling a PCI Express design in the Quartus® II software for Cyclone® V devices? Description The following error message is due to incorrect nPERST pin placement in the PCI Express Intel® FPGA IP core. For example, you will get this error message if you use pin nPERSTL0 with the bottom left HIP in Cyclone® V devices. Error (175001): Could not place Hard IP Info (175028): The Hard IP name: <top level instantiation>|altpcie_cv_hip_ast_hwtcl:dut|altpcie_av_hip_ast_hwtcl:altpcie_av_hip_ast_hwtcl| altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|arriav_hd_altpe2_hip_top Error (10104): Unable to find a path between I/O pad and PINPERST port of PCI Express Hard IP. Error (10151): "HIP_X1_Y15_N0" is not a legal location for "I/O pad" connected to PINPERSTN of PCI Express Hard IP. Info (10371): 2 potential locations for I/O pad: PIN_W24, PIN_Y23. Info (175029): 1 location affected Info (175029): HIP_X1_Y15_N0 Resolution The correct mapping for nPERSTL0 and nPERSTL1 in a Cyclone® V device is: Bottom PCIe Hard IP --> nPERSTL1 Top PCIe Hard IP --> nPERSTL0 This mapping is opposite for Stratix® V and Arria® V devices where the bottom PCIe Hard IP is associated with nPERSTL0 and the top PCIe Hard IP is associated with nPERSTL1 . Custom Fields values: ['novalue'] Troubleshooting 1408015868 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 12.1.1 ['Cyclone® V GT FPGA', 'Cyclone® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']