Why is the Intel® Stratix® 10 HPS held in reset after a reconfiguration with a partially signed image? - Why is the Intel® Stratix® 10 HPS held in reset after a reconfiguration with a partially signed image? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1 and patch 0.06, you may observe that the HPS will not come out of reset in a design where authentication is needed when configuring a signed bitstream after configuring a partially signed or unsigned bitstream. Resolution To work around this issue perform a power-on reset (POR). This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2. Custom Fields values: ['novalue'] Troubleshooting 22013068451 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 21.1 ['Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']