Why is the SDC file list order automatically rearranged in Agilex™ designs with F-Tile IP? - Why is the SDC file list order automatically rearranged in Agilex™ designs with F-Tile IP? Description During the Support-Logic generation stage, the Quartus™ Prime Pro Edition Software re-orders the precedence of SDC (Synopsys Design Constraints) files in projects where any F-tile IP is instantiated. This adjustment is made to prevent unexpected failures resulting from an incorrect SDC order. It's important to note that this behavior is not indicative of an error. However, it can lead to errors when defining constraints based on clocks generated during the Tile Logic Generation stage. This is because the constraints may target clocks that have not yet been defined after the Logic Generation stage based on the new SDC order. Resolution If you need to derive your own constraints from Tile clocks for any reason, follow the steps below: Run IP Generation and Support-Logic Generation stages. Using GUI, go to Assignments > Settings > Timing Analyzer and use the "Up" and "Down" buttons to re-arrange the files as needed ; otherwise, open your QSF (Quartus Settings File) file and re-arrange the SDC files order. Run the next compilation stages: Analysis and Synthesis, Fitter, and Assembler. Custom Fields values: ['novalue'] Troubleshooting 15014320631 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']