Why does the PLL Usage Summary report minimum and maximum lock values that are outside of my input clock frequency? - Why does the PLL Usage Summary report minimum and maximum lock values that are outside of my input clock frequency? Description The PLL Usage Summary shows the PLL Freq Min Lock and PLL Freq Max Lock values which are considered the lock range of the PLL. The input frequency must be between these two values. However, due to an issue in the Quartus® II software version 12.0 and previous versions, the PLL input clock frequency may be outside of the lock range when the PLL is configured in integer mode. This is due to an invalid PFD frequency being allowed for the PLL parameterization as described in the related solution below. Resolution Use the fractional PLL mode option in the Altera_PLL megafunction. This issue is fixed in the Quartus II software version 10.0. Related Articles Why is the reported PFD frequency in the PLL Usage Summary over the specification stated in the device data sheet? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 11.1.1 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']