Why is Riviera* (VHDL and Verilog) simulation failing for the F-tile Dynamic Reconfiguration Suite IP designs? - Why is Riviera* (VHDL and Verilog) simulation failing for the F-tile Dynamic Reconfiguration Suite IP designs? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3 and 24.3.1, you may see Riviera* (VHDL and Verilog) simulation failure or be in the hung state waiting for a signal, for the F-tile Dynamic Reconfiguration Suite IP designs with the following configurations: ) Ethernet to CPRI 25G-1 with RS-FEC configuration ) Ethernet to CPRI 25G-1 with RS-FEC (with 1GE) ) Ethernet to CPRI 25G-1 PTP with RS-FEC (with 1GE PTP) configuration Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.1. Custom Fields values: ['novalue'] Errata 14024372189, 14022459158, 22020000484 False ['F-Tile Dynamic Reconfiguration Suite IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']