A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. - A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hi Altera Comunity et al, I guess this is more of a question for the support and moderator people of this forum. The situation is I just posted a topic explaining a problem I am experiencing with Cyclone V SoC—U-boot failing to load the .rbf (FPGA load configuration ) file , during initial system bootup. I put a lot of information - attached files, links, etc. to give better context around the issue. But that post got flagged as Spam and got rejected. And I am just wondering what to do here. I tried editing that post (removing links and removing attached files) several times already, but it still stays flagged as spam. I don't know what to do further to fix this :( The original issue topic was : "Cyclone-V-SoC: U-Boot fails to fpga load .rbf file - Command 'load' failed: Error -6" Anyone, please advise. Thank you and Best Regards, - Monk M. Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Wow! I wasn't expecting that resolution! Great job debugging, both of you! Board problems can be so difficult to find! Sue Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, Thank you for the update. I'm glad to hear that so I will close this ticket. Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello Yoshiaki, Thank you so much for taking the effort to test the .rbf files I built and shared on your own DE10-Nano system, and confirming them that they actually work. :) On my side, on my own QMTECH board, I did the check (performed the register read from U-Boot shell) of the 'stat' register of the FPGA Manager Module, and I think I found my answer/reason for my troubles. So I had set MSEL SW to '01010' (ON-OFF-ON-OFF-ON) on my board, stopped at U-Boot, issued the command and got the below: => md ff706000 1 ff706000: 00000058 X... => So, I do NOT get the expected: 'ff706000: 00000050 P...' , but actually 'ff706000: 00000058 X...' . And then I checked my board physically , toggling one pin at a time , and then reading back the 'stat' register after each pin change. And it was found out that one of the pad pins (the PIN.5) of the DIP SW was broken. And toggling the one switch adjacent to that pin, made no change in the 'stat' register readout. So, I think the cause had been found for why Uboot can't load compressed .rbf succesfully - my board has a broken MSEL DIP SW pin and it just physically cannot apply/provide the MSEL = '01010'. So, I have to fix my board in this case. Anyway, at this point, I think the issue is to be considered SOLVED. You can close this ticket. Much gratitutes Yoshiaki, you've been of great help! Best Regards, - Monk M. Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, Could you please read the stat register below in FPGA Manager on U-boot? https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410067797024.html Bit Fields 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved msel RO 0x8 mode RW 0x5 The MSEL state is assigned to the STAT register of the FPGA Manager. Hit any key to stop autoboot: 0 => md ff706000 1 ff706000: 00000050 P... In this case, actual MSEL is 01010 so that the stat shows correct value. Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, Thank you for the response. We tried your RBFs and Altera's generated RBFs on DE10 Nano. All files meet our expectation. Here is summary of our test. MSEL setting on DE10 Nano is 01010 (FFPx32, Compressed enabled, Fast). No File Name Size Compression Note Result 1 soc_system.rbf 2082500 ON Altera generated No error 2 soc_system_uc.rbf 7007204 OFF Altera generated Command 'load' failed: Error -6 3 soc_system_compressed.rbf 2085508 ON You provided No error 4 soc_system_uncompressed.rbf 7007204 OFF You provided Command 'load' failed: Error -6 Here is actual of log. U-Boot 2025.07-g35abb4f1cedc-dirty (May 20 2026 - 14:25:09 +0900) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) DRAM: 1 GiB Core: 33 devices, 18 uclasses, devicetree: separate MMC: dwmmc0@ff704000: 0 Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, us ing default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Warning: ethernet@ff702000 (eth0) using random MAC address - c6:29:02:56:1d:dd eth0: ethernet@ff702000 Hit any key to stop autoboot: 0 => fatls mmc 0:1 2082500 soc_system.rbf 2085508 soc_system_compressed.rbf 7007204 soc_system_uc.rbf 154 u-boot.scr 7007204 soc_system_uncompressed.rbf 5 file(s), 0 dir(s) => load mmc 0:1 ${loadaddr} soc_system.rbf 2082500 bytes read in 105 ms (18.9 MiB/s) => fpga load 0 ${loadaddr} $filesize => load mmc 0:1 ${loadaddr} soc_system_uc.rbf 7007204 bytes read in 352 ms (19 MiB/s) => fpga load 0 ${loadaddr} $filesize Command 'load' failed: Error -6 => load mmc 0:1 ${loadaddr} soc_system_compressed.rbf 2085508 bytes read in 106 ms (18.8 MiB/s) => fpga load 0 ${loadaddr} $filesize => load mmc 0:1 ${loadaddr} soc_system_uncompressed.rbf 7007204 bytes read in 352 ms (19 MiB/s) => fpga load 0 ${loadaddr} $filesize Command 'load' failed: Error -6 => Based on the above result, your generated files were verified on DE10-Nano. Difference between your and our environment is U-boot version. You and we use 2024.07 and 2025.07, respectively. Could you please try the latest U-boot? See https://altera-fpga.github.io/rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/#2b-prepare-u-boot Lastly, could you please measure the actual voltage of MSEL pins using a voltmeter? Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hi again, Well, the photo is taken directly from QMTECH's github repo: https://github.com/ChinaQMTECH/QMTECH_Cyclone_V_SoC_KFB_With_Dual_SDRAM/blob/main/QMTECH_Cyclone_V_SoC_KFB_with_Dual_SDRAM_How_to.pdf Which could be depicting a wrong MSEL layout, but , as I said I tried different combinations of MSEL DIP SW settings - with different reading/treating the bit positions regarding MSEL [4:0] . So I tried treating/counting from the pin 5 side as MSEL[0] . Then when that didn't work, tried with treating/counting from the pin 1 side as MSEL[0]. And that didn't work either. And with both readings/side representations - I've tried all kind of MSEL combinations and nothing worked with the compressed .rbf - that I provided in the .zip of my previous post. At this point I am lost, something is not right, but I can't figure out what :( I just start to thing if my UBoot is not broken - even though it can load uncompressed .rbf. Or something is wrong the way I create the .rbf. :/ Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, Thank you for sharing the photo with us. Accdoring to a part of QMTECH_Cyclone_V_SoC_KFB_Dual_SDRAM_Schematic_20240607_V01.pdf below , MSEL order is opposite compared to your photo. Here are pin assignments for MSEL. SW5.1:MSEL0 SW5.2:MSEL1 SW5.3:MSEL2 SW5.4:MSEL3 SW5.5:MSEL4 Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hi Yoshiaki, Darn, I forgot to attach my files earlier. Anyway, here they are now - check the 'soc_system_files.zip'. I have the uncompressed .sof, uncompressed .rbf , the compressed .rbf utilizing the .cof file. Also I put my .qsf file for additional info. Thanks for continue to look into this, I just wonder do you have a Terasic DE10-Nano board, somewhere around you to test? In addition, I've attached a zip of my .img file that I use to write to my SD Card and boot on my board - it features the compressed .rbf file, that fails to load properly on my board. FYI, I am aware of the MSEL settings for the board : - but whatever DIP SW combination I try, I always get this error -6 :( Hope this helps. :/ Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, Thank you for testing .rbf again. We have verified .rbf with/without compress mode on Cyclone V SoC DevKit. Please double check of MSEL setting. Accdoring to QMTECH_Cyclone_V_SoC_KFB_Dual_SDRAM_Schematic_20240607_V01.pdf, Please keep in mind to set SW5 for MSEL to ON to represent 0 and to OFF to represent 1. Next , here are commands to generate .rbf from .sof. quartus_cpf -c -o bitstream_compression=on soc_system.sof soc_system_comp_on.rbf quartus_cpf -c -o bitstream_compression=off soc_system.sof soc_system_comp_off.rbf Here are actual logs on Cyclone V SoC Dev Kit. In case of MSEL = 01000 (FPPx32, Compress Off, Fast) U-Boot SPL 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900) DDRCAL: Scrubbing ECC RAM (1024 MiB). DDRCAL: SDRAM-ECC initialized success with 578 ms Trying to boot from MMC1 U-Boot 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) DRAM: 1 GiB Core: 33 devices, 18 uclasses, devicetree: separate MMC: dwmmc0@ff704000: 0 Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Warning: ethernet@ff702000 (eth0) using random MAC address - 4e:4c:9a:70:2d:81 eth0: ethernet@ff702000 Hit any key to stop autoboot: 0 => load mmc 0:1 ${loadaddr} soc_system_comp_on.rbf 2356140 bytes read in 120 ms (18.7 MiB/s) => fpga load 0 ${fileaddr} $filesize Command 'load' failed: Error -6 => load mmc 0:1 ${loadaddr} soc_system_comp_off.rbf 7007204 bytes read in 351 ms (19 MiB/s) => fpga load 0 ${fileaddr} $filesize => In case of MSEL = 01010 (FPPx32, Compress ON, Fast) U-Boot SPL 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900) DDRCAL: Scrubbing ECC RAM (1024 MiB). DDRCAL: SDRAM-ECC initialized success with 579 ms Trying to boot from MMC1 U-Boot 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) DRAM: 1 GiB Core: 33 devices, 18 uclasses, devicetree: separate MMC: dwmmc0@ff704000: 0 Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Warning: ethernet@ff702000 (eth0) using random MAC address - 1e:b9:e6:16:1a:1c eth0: ethernet@ff702000 Hit any key to stop autoboot: 0 => load mmc 0:1 ${loadaddr} soc_system_comp_on.rbf 2356140 bytes read in 120 ms (18.7 MiB/s) => fpga load 0 ${fileaddr} $filesize => load mmc 0:1 ${loadaddr} soc_system_comp_off.rbf 7007204 bytes read in 351 ms (19 MiB/s) => fpga load 0 ${fileaddr} $filesize Command 'load' failed: Error -6 => Lastly, please upload your .sof file. Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hi, here's an update: I've tried again to generate compressed bitstream files (.rbf) and then feed it - to be loaded by UBoot, during boot-up. At the beginning, I took the uncrompressed .sof file created when building the Quartus HW project, and then used the 'Convert Programming Files...' tool , to convert and compress the .sof file into .rbf file, using the following settings: And then used the created .rbf file to create a bootable and SD Card .img file. And then set the MSEL [4:0] switches = '00010' and '00110' , according to the table: And then I tried all kinds of combinations , including the ones you posted: Mode MSEL Compression POR Delay FPPx16 00010 Enabled Fast FPPx32 01010 Enabled Fast FPPx16 00110 Enabled Standard FPPx32 01110 Enabled Standar And still , when booting the image, I get the ' Command 'load' failed: Error -6' error , when Uboot is loading the .rbf file. :( What I am supposed to do here, to get compressed FPGA configs to be booted? I am lost.... (I've attached a .zip file, containng my .sof, .rbf and .cof files used). Note: The board that I am using is a (QMTECH Cyclone V SoC board) clone of Terasic's DE10-Nano, so the provided (attached here) .rbf file is to be compatible with the Terasic's board. The .rbf file contains the hw design of the DE10-Nano GHRD project, from the provided Demo Projects by Terasic. So nothing special. Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, Thank you for the update. I'm glad to hear .rbf without compression works fine. Could you please try the following combination? Mode MSEL Compression POR Delay FPPx16 00010 Enabled Fast FPPx32 01010 Enabled Fast FPPx16 00110 Enabled Standard FPPx32 01110 Enabled Standard Table 27. Configuration Schemes for FPGA Configuration by the HPS https://docs.altera.com/r/docs/683126/21.2/cyclone-v-hard-processor-system-technical-reference-manual/fpga-configuration?tocId=oT8kgUpEZokq8aJ3ItYu8g Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Then, I took the .rbf file (from the prev post) and put in (overwriting the older .rbf file) to the FAT partion of the SD Card, and set the MSEL [4:0] = '00000' (All are 'ON' ) , and powered up the board. And this time there were no errors when loading the .rbf. U-Boot SPL 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300) Trying to boot from MMC1 U-Boot 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) DRAM: 1 GiB Core: 29 devices, 15 uclasses, devicetree: separate MMC: dwmmc0@ff704000: 0 Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: QMTECH C5SOC KFB Dual SDRAM Net: Error: ethernet@ff702000 No valid MAC address found. No ethernet found. Hit any key to stop autoboot: 0 => => fpga info Altera Device Descriptor @ 0x3ffec7a0 Family: SoC FPGA Interface type: Fast Passive Parallel (FPP) Device Size: 4294967295 bytes Cookie: 0x0 (0) No Device Function Table. => fatls mmc 0:1 6275664 zImage extlinux/ 7007204 soc_system.rbf 25844 socfpga_cyclone5_kfb_dual_sdram.dtb 3 file(s), 1 dir(s) => oad mmc 0:1 ${loadaddr} soc_system.rbf; Unknown command 'oad' - try 'help' => load mmc 0:1 ${loadaddr} soc_system.rbf; 7007204 bytes read in 363 ms (18.4 MiB/s) => fpga load 0 ${loadaddr} $filesize; => And after the .rbf was loaded, the JTAG nodes showed up again when polled , through the NIOS shell with the USB Blaster: ~$ jtagconfig -n 1) USB-Blaster [1-4] 4BA00477 SOCVHPS 02D020DD 5CSEBA6(.|ES)/5CSEMA6/.. Design hash 385F96C94BBA3F772A79 + Node 0C206E00 JTAG PHY #0 + Node 0C206E01 JTAG PHY #1 + Node 0C206E02 JTAG PHY #2 + Node 0C006E00 JTAG UART #0 + Node 00486E00 Source/Probe #0 So, at this point, I have a functioning FPGA configuration loading when UBooting. Note this is with uncompressed bitstream files. I guess the next thing that remains to check - is why and how to make the original attempt with compressed bitstream file (.rbf) to work :? Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Greetings Yoshiaki, So, first, I actually tried something first yesterday after writing my original message and I have good results. In the Quartus project settings - I disabled the compression for the bitstream and also set the Configuration scheme to Passive Parallel x16. Also, in the same project settings, I enabled the generation of the Raw Binary File (.rbf). So, now when the Quartus project is rebuild (as normal) it will also create the .rbf file I need for U-boot. Then I recompiled the project, and just used to .sof file to program directly the FPGA part of the device: And it was all successful. Actually, the FPGA portion of the design contains a Qsys, that features several different JTAG masters and JTAG Uart. And after the design (.sof) was programmed - those became visible when polling the jtagconfig with the USB-Blaster still attached: Thus, the configuration files (.sof) and (.rbf) - match and work with the SoC FPGA on the board correctly. Note: At this point the produced .sof and .rbf files are 'uncompressed' and configured for 'FPP x16'. Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, The issue was happened on the following code. https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2026.01/drivers/fpga/socfpga_gen5.c#L158 static int fpgamgr_program_poll_initphase(void) { unsigned long i; /* Additional clocks for the CB to enter initialization phase */ if (fpgamgr_dclkcnt_set(0x4)) return -5; /* (4) wait until FPGA enter init phase or user mode */ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) break; if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) break; } /* If not in configuration state, return error */ if (i == FPGA_TIMEOUT_CNT) return -6; return 0; } This issue most likely is happened on the mismatch of MSEL and generated RBF, or Device OPN mismatch. 1) Check SOF. Please configure your SOF by Quartus Programmer via JTAG. If it fails, Device OPN is incorrect. Please update DEVICE section in your qmtech_c5soc_kfb_dual_sdram_ghrd.qsf. 2) Check the compression mode of the RBF. Here are details of the settings. MSEL Configuration Scheme Compression 00000 FPPx16 Disabled 01010 FPPx32 Enabled 3) Check your power supply. Does the output current of your power supply meet requirement of the board? Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Hello monkstein88, We apologize for the inconvenience. I will check the original topic. Best regards, Yoshiaki Saito Replies: Re: A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected. Ok, I will try to lay out the original problem I have been encountering. Currently I am experiencing a persistent issue with a QMTech Cyclone V SoC board (a very close clone of the Terasic DE10-Nano Board), trying to load the fpga configuration (.rbf) while the board is booting (U-Boot). While the .rbf is being loaded, I get an error: 'Command 'load' failed: Error -6' . Overall, the whole booting process works, my system is able to go through the whole process: UBoot SPL -> UBoot -> Linux (logjn prompt). But a phase in between - which is the FPGA configuration loading is failing. Here's the U-Boot shell excerpt, where I prompt the system for a couple of things and then try to fpga load the .rbf file: => fpga info Altera Device Descriptor @ 0x3ffec7a0 Family: SoC FPGA Interface type: Fast Passive Parallel (FPP) Device Size: 4294967295 bytes Cookie: 0x0 (0) No Device Function Table. => => printenv arch=arm baudrate=115200 board=c5soc-kfb-dual-sdram board_name=c5soc-kfb-dual-sdram boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr} boot_efi_binary=load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootarm.efi; if fdt addr -q ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r};else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi boot_efi_bootmgr=if fdt addr -q ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr;fi boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf} boot_net_usb_start=usb start boot_prefixes=/ /boot/ boot_script_dhcp=boot.scr.uimg boot_scripts=boot.scr.uimg boot.scr boot_syslinux_conf=extlinux/extlinux.conf boot_targets=mmc0 qspi pxe dhcp bootcmd=load mmc 0:1 ${loadaddr} soc_system.rbf && fpga load 0 ${loadaddr} $filesize; sysboot mmc 0:1 any ${scriptaddr} /extlinux/extlinux.conf bootcmd_dhcp=devtype=dhcp; run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; fi; setenv efi_old_vci ${bootp_vci};setenv efi_old_arch ${bootp_arch};setenv bootp_vci PXEClient:Arch:00010:UNDI:003000;setenv bootp_arch 0xa;if dhcp ${kernel_addr_r}; then tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};if fdt addr -q ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r}; else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi;fi;setenv bootp_vci ${efi_old_vci};setenv bootp_arch ${efi_old_arch};setenv efi_fdtfile;setenv efi_old_arch;setenv efi_old_vci; bootcmd_mmc0=devnum=0; run mmc_boot bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi bootcmd_qspi=run qspiload; run qspiboot bootdelay=2 bootm_size=0xa000000 bootmode=sd cpu=armv7 distro_bootcmd=for target in ${boot_targets}; do run bootcmd_${target}; done efi_dtb_prefixes=/ /dtb/ /dtb/current/ fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};then source ${scriptaddr}; fi fdt_addr_r=0x02000000 fdtcontroladdr=3bf74610 fdtfile=socfpga_cyclone5_kfb_dual_sdram.dtb fpgatype=cv_se_a6 kernel_addr_r=0x01000000 load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile} loadaddr=0x01000000 mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi mtdids=nor0=ff705000.spi.0 prog_core=if load mmc 0:1 ${loadaddr} fit_spl_fpga.itb;then fpga loadmk 0 ${loadaddr}:fpga-core-1; fi pxefile_addr_r=0x02200000 ramdisk_addr_r=0x02300000 scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_dev_for_efi; scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then part uuid ${devtype} ${devnum}:${distro_bootpart} distro_bootpart_uuid ; run scan_dev_for_boot; fi; done; setenv devplist scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; fi; for prefix in ${efi_dtb_prefixes}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${efi_fdtfile}; then run load_efi_dtb; fi;done;run boot_efi_bootmgr;if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/bootarm.efi; then echo Found EFI removable media binary efi/boot/bootarm.efi; run boot_efi_binary; echo EFI LOAD FAILED: continuing...; fi; setenv efi_fdtfile scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefix}${boot_syslinux_conf}; run boot_extlinux; echo EXTLINUX FAILED: continuing...; fi scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done scriptaddr=0x02100000 scriptfile=u-boot.scr soc=socfpga socfpga_legacy_reset_compat=1 stderr=serial stdin=serial stdout=serial usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi vendor=qmtech ver=U-Boot 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300) Environment size: 4441/8188 bytes => => => fatls mmc 0:1 6275664 zImage extlinux/ 2082772 soc_system.rbf 25844 socfpga_cyclone5_kfb_dual_sdram.dtb 3 file(s), 1 dir(s) => load mmc 0:1 ${loadaddr} soc_system.rbf; 2082772 bytes read in 111 ms (17.9 MiB/s) => fpga load 0 ${loadaddr} $filesize; Command 'load' failed: Error -6 => => I've attached a zip which contains a full boot log, defconfig and .config file produced after building U-Boot. Also pics of what my Quartus projects settings are - regarding the generated and used .rbf file. FYI, I've tried several MSEL Dip Sw settings : "00000" and "01010" but nothing works. Please advise :? -Monk - 2026-05-09