Why is there an incorrect output port instead of inout port for bidirectional port in simulation netlist (.vho/.vo) files ? - Why is there an incorrect output port instead of inout port for bidirectional port in simulation netlist (.vho/.vo) files ? Description Due to a problem in the Quartus® Prime Standard Edition Software version 17.1 and earlier, you may see an incorrect output port instead of inout port for bidirectional port in simulation netlist (.vho/.vo) files. This occurs when you recompile of your design on a linux machine. Resolution To workaround the problem, clean the project before running compilation. Custom Fields values: ['novalue'] Troubleshooting FB: 511956; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 17.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']