You will see this error on Stratix® V and Arria® V devices when connecting an incorrectly configured fPLL output clock to a transceiver Native PHY IP configured external PLL mode. - You will see this error on Stratix® V and Arria® V devices when connecting an incorrectly configured fPLL output clock to a transceiver Native PHY IP configured external PLL mode. Description You will see this error on Stratix® V and Arria® V devices when connecting an incorrectly configured fPLL output clock to a transceiver Native PHY IP configured external PLL mode. Error Message: Error: Clock Divider parameter 'data_rate' is set to an illegal value of 'xxxx.x Mbps' on node 'native_phy_top:inst|altera_xcvr_native_sv:native_phy_top_inst|sv_xcvr_native:gen_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'.Info: "xxx.x Mbps" is a legal value Resolution The fPLL should be configured for half the frequency of the Native PHY data rate for correct operation. Custom Fields values: ['novalue'] Troubleshooting NA False ['PLL'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix No plan to fix ['Arria® V GX FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']