Why does the Intel® Quartus® Prime Timing Analyzer ignore the timing constraints for the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express*? - Why does the Intel® Quartus® Prime Timing Analyzer ignore the timing constraints for the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express*? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2 and earlier, the Intel® Quartus® Prime Timing Analyzer will ignore the timing constraints for the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* if you have a generate statement used in your VHDL or Verilog code to create the IP in your design. This problem occurs because the generate statement will create a “\” as the hierachy path that is not recognized by the Intel Arria 10/Cyclone 10 Hard IP for PCI Express* SDC (Synopsys* Design Constraint) files. Resolution To work around this problem, download the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* SDC file and replace the altera_pci_express.sdc in <project_name>/<pcie_name>/altera_pcie_a10_hip/synth. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507229887 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']