Agilex 5 SDI 148.5 and 148.35 MHz refclks - Agilex 5 SDI 148.5 and 148.35 MHz refclks I'm working on a design for the Agilex 5 that is going to need to be able to switch between integer and fractional framerates, and I'm trying to figure out and understand the clocking structure involved. In the GTS SDI II IP User Guide, there is a set of parameters for "Transceiver reference clock frequency" and "Dynamic TX clock switching" under the category "Transceiver Options", however I don't see these parameters in Quartus. Is there somewhere else that I can enable this option to have the two different reference clock frequencies? Do I need this enabled, or is there some other way that I can switch between the two frequencies? In addition, what does the clocking structure look like to do this? Is there a way to provide 148.5 MHz to the board and then generate the 148.35 from a PLL to be multiplexed? Or do I need to provide both clock frequencies separately? If I need to provide both clock frequencies separately, what pins can I use for the 148.35 MHz reference clock? The two differential pairs of reference clocks for the GTS bank are already being used for the System PLL reference clock and the 148.5 MHz. Any help with these questions would be greatly appreciated. Replies: Re: Agilex 5 SDI 148.5 and 148.35 MHz refclks Hi yuriah726 , If I am going to have my own board instead of a devkit, then I will need to provide the FPGA with a reference clock signal that is multiplexed between 148.5 and 148.35 MHz, as well as implement the multiplexing control. Is this correct? >> Yes. For Agilex 5 TX-only SDI, the expected approach is to externally select either 148.5 MHz or 148.35 MHz and feed that selected clock to the transceiver reference clock input. Is there a way to provide both reference clocks to the IP and switch between them internally? >> No. There is no Agilex 5 SDI II IP option in Quartus for internal switching between two reference clocks. Hope this clarified. Regards, Wincent_Altera Replies: Re: Agilex 5 SDI 148.5 and 148.35 MHz refclks Hi Wincent_Altera , I just want to make sure I am understanding correctly. If I am going to have my own board instead of a devkit, then I will need to provide the FPGA with a reference clock signal that is multiplexed between 148.5 and 148.35 MHz, as well as implement the multiplexing control. Is this correct? There isn't a way to provide both reference clocks to the IP and switch between them, or provide one and generate the other from it? Once again, this is for transmitting SDI data, not receiving, so I'm not trying to detect whether the framerate is being sent to me as fractional or integer, but rather make the framerate I am transmitting be fractional or integer. Thank you very much for all of your help, Yuriah Replies: Re: Agilex 5 SDI 148.5 and 148.35 MHz refclks Hi yuriah726 , There is a mistake in the user guide, got GTS SDI II for Agilex 5 , user do not need to change this. Please set either 148.5 / 148.35 thru clock control of dip_switch control. The rx phy have the tolerance to accept both 148.5 and 148.35. Hope this clarified. Regards, Wincent_Altera Replies: Re: Agilex 5 SDI 148.5 and 148.35 MHz refclks Hi Wincent, Thank you very much for your reply. May I know which page / section you are looking for this information ? >> Section 4, table 9 at: https://docs.altera.com/r/docs/823539/25.3/gts-sdi-ii-ip-user-guide/gts-sdi-ii-ip-parameters Altera recommends you not to share TX PLL reference clock with RX transceiver reference clock for a parallel loopback design because TX PLL clock is going to be tuned to match RX recovered clock frequency. >> I am only doing the TX side with no RX. I need to be able to transmit SDI at both integer and fractional framerates. it depends on the device actually , but you can refer to our design example targeted the Agilex5 devkit, that can be a good reference to map the pin >> I believe I'm looking at the correct reference design, but the only thing it mentions about switching between 148.35 and 148.5 MHz (or their doubles for Tx) is that it can be programmed in the clock GUI. In my application, this is going to need to be able to be changed while the design is in operation, either through RTL or external hardware. Thank you for your help, Yuriah Replies: Re: Agilex 5 SDI 148.5 and 148.35 MHz refclks Hi yuriah726 , In the GTS SDI II IP User Guide, there is a set of parameters for "Transceiver reference clock frequency" and "Dynamic TX clock switching" under the category "Transceiver Options", however I don't see these parameters in Quartus. Is there somewhere else that I can enable this option to have the two different reference clock frequencies? Do I need this enabled, or is there some other way that I can switch between the two frequencies? >> May I know which page / section you are looking for this information ? >> Just trying to understand more so that we can speak apple to apple Or do I need to provide both clock frequencies separately? If I need to provide both clock frequencies separately, >> Altera recommends you not to share TX PLL reference clock with RX transceiver reference clock for a parallel loopback design because TX PLL clock is going to be tuned to match RX recovered clock frequency. If I need to provide both clock frequencies separately, what pins can I use for the 148.35 MHz reference clock? >> it depends on the device actually , but you can refer to our design example targeted the Agilex5 devkit, that can be a good reference to map the pin >> Also you can refer to https://www.altera.com/design/devices/resources/pinouts#tab-blade-1-3 Regards, Wincent_Altera