{*Name Protected*} (*/stratixv_atoms.vhd: line 5355, position 21) and verilog parameter being overridden {*Name Protected*}.{*Name Protected*} (*/stratixv_atoms_ncrypt.v: line -1, position -1) are not type compatible. - {*Name Protected*} (*/stratixv_atoms.vhd: line 5355, position 21) and verilog parameter being overridden {*Name Protected*}.{*Name Protected*} (*/stratixv_atoms_ncrypt.v: line -1, position -1) are not type compatible. Description You may see this error when simulating a VHDL design in the Cadence NC-Sim software if the VHDL instantiates lower level Verilog HDL files. Resolution To avoid this error, use the -namemap_mixgen option with the ncelab command. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']