Some Low Latency 40-100GbE IP Core 100GbE Variations Have Lower Than Expected Bandwidth Because of Wrong Value in IPG_COL_REM Register - Some Low Latency 40-100GbE IP Core 100GbE Variations Have Lower Than Expected Bandwidth Because of Wrong Value in IPG_COL_REM Register Description The Low Latency 40-100GbE IP core IPG_COL_REM register at offset 0x406 should have the value of 20 decimal in 100GbE variations and the value of 4 decimal in 40GbE variations. However, the LL 40-100GbE IP core v14.1 sets this register to the value of 4 in 100GbE variations. This issue applies to all LL 100GbE IP cores for which you specify an inter-packet gap in the LL 40-100GbE parameter editor. This issue reduces the bandwidth of the LL 100GbE IP core. Resolution To work around this issue and correct the interpacket gap , write the value of 20 decimal to the IPG_COL_REM register in your LL 100GbE IP core variation. This issue is fixed in version 15.0 of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Ethernet'] ['FPGA Dev Tools Quartus II Software'] 15.0 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']