RapidIO II IP Core Might Erroneously Declare a Port Error - RapidIO II IP Core Might Erroneously Declare a Port Error Description The RapidIO II IP core declares a port error when it times out waiting for a link request in the stop_input state of the input port error recovery state machine. However, the input port error recovery state machine should not cause the IP core to declare a port error. The RapidIO v2.2 specification does not require a timeout in this situation. Resolution This issue has no workaround. This issue is fixed in version 13.0 SP1 of the RapidIO II MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']