Is there any known issue for EPE for DDR3 IO? - Is there any known issue for EPE for DDR3 IO? Description When customer use EPE 11.1sp1 and estimate DDR3 interface, the IO standard is SSTL-18 in EPE. The correct standard should be SSTL-15. This bug would be fixed in 11.1sp2. Resolution Fixed in 11.1sp2 Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1.2 11.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']