Why do I see JTAG problems when using the Signal Tap II logic analyzer with the Intel® Quartus® Prime Pro Edition Software? - Why do I see JTAG problems when using the Signal Tap II logic analyzer with the Intel® Quartus® Prime Pro Edition Software? Description In the Intel® Quartus® Prime Pro Edition Software, the JTAG signals are no longer automatically constrained. As a result of this, you might experience triggering problems using the Signal Tap II logic analyzer and any other tools using the JTAG interface. Resolution Apply the following timing assignments example to ensure correct functionality of the JTAG interface: create_clock -name altera_reserved_tck -period 10 [get_ports altera_reserved_tck] #cut all paths to and from altera_reserved_tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] # I/O min delays set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdi] -min 2 set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tms] -min 2 set_output_delay -clock altera_reserved_tck [get_ports altera_reserved_tdo] -min 3 # I/O max delays set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdi] -max 3 set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tms] -max 3 set_output_delay -clock altera_reserved_tck [get_ports altera_reserved_tdo] -max 4 Note that the values specified in the constraints above are arbitrary values. You should ensure that the values you specify match the destination hardware. Custom Fields values: ['novalue'] Troubleshooting FB: 322266; False ['Signal Tap Logic Analyzer IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.1 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']