Are there any issues when a host CPU triggers full chip reconfiguration via PCIe or when using CvP for Intel® Stratix® 10 devices in Intel® Quartus® Prime Pro Edition software version 20.3? - Are there any issues when a host CPU triggers full chip reconfiguration via PCIe or when using CvP for Intel® Stratix® 10 devices in Intel® Quartus® Prime Pro Edition software version 20.3? Description Due to a problem in the Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express® IP core in Intel® Quartus® Prime Pro Edition software version 20.3, you may see following issues: 1. PCIe BARs are not accessible after core configuration in Configuration via Protocol (CvP) design; 2. Host system hangs and auto restarts when host CPU triggers full-chip reconfiguration via PCIe, such as Remote System Update (RSU) over PCIe. Resolution This issue has been fixed in Intel® Quartus® Prime Pro Edition software version 20.4 and later. You can also install the following patch for Intel® Quartus® Prime Pro Edition software version 20.3, : quartus-20.3-0.28-readme.txt quartus-20.3-0.28-linux.run quartus-20.3-0.28-windows.exe Custom Fields values: ['novalue'] Troubleshooting 18013485866 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 20.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']