Why are the Arria 10 DDR4 Mode Register 4 (MR4) write/read preamble bits set incorrectly? - Why are the Arria 10 DDR4 Mode Register 4 (MR4) write/read preamble bits set incorrectly? Description There is a known issue in the Quartus® II software version 13.1 Arria 10 Edition where the DDR4 MR4 write/read preamble bits are set incorrectly. Resolution The issue is fixed in the Quartus II software version 14.0 Arria 10 Edition. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0a10 13.1a10 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']