Why is there a mismatch in the FFT Intel® FPGA IP output result in simulation between the IP-generated MATLAB* model and the HDL model? - Why is there a mismatch in the FFT Intel® FPGA IP output result in simulation between the IP-generated MATLAB* model and the HDL model? Description Due to a problem with the FFT Intel® FPGA IP version 19.1, you may observe the above problem in the simulation if the Data Output Width of the IP is not configured to the maximum supported width. Resolution To work around this problem configure the Data Output Width to the maximum supported width in IP. This problem is currently not scheduled to be fixed in a future version of the FFT Intel® FPGA IP. Custom Fields values: ['novalue'] Troubleshooting 1508145050 False ['FFT IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 19.1 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']