Why can't I place a DDR3 UniPHY-based controller in quadrant 1 or 2 in a Cyclone® V or Arria® V SoC device? - Why can't I place a DDR3 UniPHY-based controller in quadrant 1 or 2 in a Cyclone® V or Arria® V SoC device? Description If you try to place a DDR3 UniPHY-based controller in quadrant 1 or 2, you will get the following errors. Error (175020): Illegal constraint of PLL output counter to the region (0, 31) to (0, 81): no valid locations in region Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region UniPHY-based controllers use dual-regional clocks for the pll_afi_clk, pll_addr_cmd_clk, and pll_config_clk signal s. This is to allow an interface to span an entire side of a device. Certain quadrants of Cyclone® V SoC and Arria® V SoC devices do not have dual-regional clocks. Resolution Placing a DDR3 UniPHY-based controller in quadrant 1 or 2 is possible. You must ensure that in the QSF file, the DDR3 controller uses regional clock assignments, instead of dual-regional clock assignments. Custom Fields values: ['novalue'] Troubleshooting 2205829539 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V FPGAs and SoCs', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']