Using Altera® SoC FPGAs: Configuration and Booting - This instructor-led class is taught in a virtual classroom over 1 half day of instruction. You will use a remote computer connected on a cloud based platform for hands-on labs. No setup is needed. Course Description The focus of this course is to design with Agilex™ 5 SoC FPGAs using the Quartus® Prime Software for these devices. It will cover the Hard Processor System (HPS) architecture for Agilex™ 5 SoC FPGAs, including an overview of the Arm* Cortex*-A76 and Arm* Cortex*- A55. You will learn to add and configure the processor component in a Platform Designer system from Quartus® Prime software and to build the first-stage and second-stage bootloaders (based on U-Boot or Arm* Trusted Firmware), and boot to the embedded OS. You will learn the boot stages for Altera® SoC FPGA SDM based devices, the supported boot flows to Linux* OS and Zephyr* RTOS as well as drivers, RTOS and single image booting. At the completion of the course, you will have the knowledge necessary to immediately start using Altera® SoC FPGA devices in your own designs or on development kits. *ARM and AMBA are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. Course Objectives At course completion, you will be able to: Create, manage, and compile an SoC based FPGA using the Platform Designer tool in Quartus® Prime Software using the GHRD Work with device tree and drivers, build applications with Zephyr* RTOS and the binaries for booting Use Linux* OS and Zephyr* with Agilex™ 5 SoC FPGA model in Altera® Simics® Simulator Skills Required FPGA knowledge and embedded OS. Previous ILT, Using Altera® SoC FPGAs: An Introduction . If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ISOC105. FPGA_ISOC104. <p>Using Altera SoC FPGAs: Configuration and Booting</p>