Why do I see DDR4 Read Capture timing violations in the Quartus Prime software version 16.0? - Why do I see DDR4 Read Capture timing violations in the Quartus Prime software version 16.0?
Description You may see Read Capture timing violations in your Arria® 10 DDR4 design after upgrading to the Quartus® Prime software version 16.0. The violations are probably due to the final Arria 10 timing models in the Quartus Prime software version 16.0. Resolution To resolve the timing violations, enable the Read DBI option in the Memory Topology tab of the DDR4 IP.
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Troubleshooting
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False
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['FPGA Dev Tools Quartus® Prime Software Pro']
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16.0
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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