Why do the tx_path_delay_10g_data and tx_path_delay_1g_data signal descriptions refer to a data width of 16/22 for the Arria® V and Stratix® V devices in the Low Latency Ethernet 10G MAC User Guide? - Why do the tx_path_delay_10g_data and tx_path_delay_1g_data signal descriptions refer to a data width of 16/22 for the Arria® V and Stratix® V devices in the Low Latency Ethernet 10G MAC User Guide? Description Due to a mistake in Table 5-16: IEEE 1588v2 Egress Transmit Signals" of the Altera® Low Latency Ethernet 10G MAC User Guide (PDF), the tx_path_delay_10g_data and tx_path_delay_1g_data signal descriptions refer to a data width of 16/22 for the Arria® V and Stratix® V devices. tx_path_delay_10g_data tx_path_delay_1g_data signal signals should refer to a data width of 15/21. Resolution This problem has already been fixed in a new version of the Low Latency Ethernet 10G MAC User Guide (PDF). Custom Fields values: ['novalue'] Troubleshooting 181248 False ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']