How should I read 36-bit counter registers of Low Latency 10GbE and Low Latency 40 - 100GbE MAC IP core to obtain correct counter value? - How should I read 36-bit counter registers of Low Latency 10GbE and Low Latency 40 - 100GbE MAC IP core to obtain correct counter value? Description To read 36-bit registers in the Low Latency 10, 40 and 100GbE MAC IP cores, read the lower 32-bit first, followed by upper 4-bit. For self-clear (RC) counter registers such as register-based counters, the lower 32-bit must be read first, followed by the upper 4-bit to obtain correct values. For non-self-clear (RO) counter registers such as memory-based counters, when the lower 32-bit are read, the upper 4-bit are captured. Therefore, the misalignment of the lower 32-bit and the upper 4-bit values due to carry to the upper 4-bit during counter read will not happen. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GZ FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']