XIP1213H, High-speed MACSEC AES-GCM IP Core targeting 10G/25G/40G linerates - XIP1213H from Xiphera is a high-speed Intellectual Property (IP) core implementing the MACsec protocol. Xiphera designs and implements hardware-based security using proven cryptographic algorithms. Our strong cryptographic expertise and extensive experience in digital system design enable us to help… Arria® 10 SX FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® III FPGA MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera’s high speed MACsec solution safeguards the confidentiality and integrity of data transmitted over point-to-point communication links up to 40G, assured by the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with runtime configurable key lengths. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation Wireless XIP1213H, High-speed MACSEC AES-GCM IP Core targeting 10G/25G/40G linerates Key Features Moderate resource requirements: The entire XIP1213H requires 54665 Adaptive Lookup Modules (ALMs) (Altera® Stratix® 10 GX), and does not require any multipliers or DSPBlocks in a typical FPGA implementation. Offering Brief Yes No No Yes Encrypted VHDL VHDL Arria® 10 SX FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® III FPGA Yes Yes 25.1.1 Offering Brief Production a1JUi0000049USpMAM What's Included Encrypted RTL or source code Ordering Information XIP1213H a1JUi0000049USpMAM Production Intellectual Property (IP) a1MUi00000BO8toMAD a1MUi00000BO8toMAD Select 2026-04-21T12:58:33.000+0000 XIP1213H from Xiphera is a high-speed Intellectual Property (IP) core implementing the MACsec protocol. Partner Solutions