Why do I get incorrect results when inferring fixed-point tensor blocks in Agilex™ 5 devices? - Why do I get incorrect results when inferring fixed-point tensor blocks in Agilex™ 5 devices? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you might see incorrect results when targeting an Agilex™ 5 device if your designs use RTL to infer fixed-point tensor blocks. The problem occurs during synthesis when bits result_h[0] , and result_l[37] of the inferred DSP block might be stuck high in hardware. The problem does not occur in RTL simulation. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.2 Custom Fields values: ['novalue'] Troubleshooting TBD False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']