Hold Time Requirement Not Met in Stratix V Devices - Hold Time Requirement Not Met in Stratix V Devices
Description Designs that target Stratix V devices may not meet hold time requirements. This issue affects all designs that targets Stratix V devices. Resolution Run a seed sweep using the Design Space Explorer.This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function.
Custom Fields values:
['novalue']
Troubleshooting
novalue
True
['Ethernet']
['FPGA Dev Tools Quartus II Software']
novalue
11.1
['Stratix® V FPGAs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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