not valid - not valid Description Due to the Intel® Arria® 10 external memory interface (EMIF) intellectual property (IP) accessing the MMR registers during the calibration phase, the mmr_readdata_valid signal assertion can be seen from the MMR slave port. This behavior can cause the MMR slave port Avalon® bus to lock up. Here is a related KDB answer: https://www.intel.com/content/www/us/en/support/programmable/articles/000085925 Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 432146; False ['External Memory Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']