Error (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in region - Error (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in region Description This error can occur in Stratix® V, Arria® V, and Cyclone® V devices when the PLL Intel® FPGA IP is sourced by a global or regional network where that network is driven by a dedicated clock input pin. The connection of a dedicated clock pin to a phase-locked loop (PLL) over a global / regional network is legal, however, the Quartus® II software will not allow this connection without an explicit promotion of the clock to the global or regional resource through a clock control block. Resolution Insert an ALTCLKCTRL Intel® FPGA IP in the clock path between the dedicated clock input pin and the PLL Intel FPGA IP. Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL Intel® FPGA IP must be instantiated in your design. This is not necessary when the clock input pin has dedicated access to the PLL Intel FPGA IP. Related Articles Error (175001): Could not place fractional PLL <PLL name> Custom Fields values: ['novalue'] Troubleshooting 2205796058 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 13.0 10.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']