Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in region Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver - Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in region Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver Description You may experience the below fitter error when compiling a UniPHY-based memory controller in Cyclone® V SoC and Arria® V SoC device. The error occurs because the FPGA device does not have dual-regional clocks in certain portions of the chips. Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in regionError (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region Resolution The workaround is to change pll_avl_clk, pll_config_clk, and pll_addr_cmd_clk from dual-regional clock to regional clock in the.QSF file as follows: From: set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_addr_cmd_clk set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_avl_clk set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_config_clk To: set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_addr_cmd_clk set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_avl_clk set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_config_clk Custom Fields values: ['novalue'] Troubleshooting 2205829539 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']