Is there a known problem with the self-reset feature when using the Altera PLL IP in Stratix V, Arria V or Cyclone V devices? - Is there a known problem with the self-reset feature when using the Altera PLL IP in Stratix V, Arria V or Cyclone V devices? Description Due to a known problem in Quartus® II software version 13.1, the self reset feature in the Altera® PLL IP may not work properly when the PLL loses lock in Stratix® V, Arria® V or Cyclone® V devices. Resolution This problem is fixed in Quartus II version 13.1 update 3. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1.3 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']