Why does the RapidIO II IP Core transmit when TX digital reset is asserted? - Why does the RapidIO II IP Core transmit when TX digital reset is asserted? Description Due to a bug in the RapidIO II IP Core, the transceiver can start transmitting 0xBC characters before TX Digital Reset ( tx_digitalreset on Arria® 10, or tx_digitalreset_stat on Stratix® 10) has been de-asserted. This can cause some link partners to incorrectly detect IDLE1 sequence. The detection of IDLE1 sequence is a defined implementation. Note that RapidIO II IP Core uses IDLE2 sequence. Resolution This problem has been fixed starting in software version 17.0 of the RapidIO II IP core. Custom Fields values: ['novalue'] Troubleshooting FB: 389461; True ['RapidIO II (IDLE2 up to 6.25 Gbaud) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']