vhdl error - vhdl error i neep to plan counter bcd library ieee; use ieee.std_logic_1164.all; entity h145 is port ( resetn: in std_logic; clk: in std_logic; sclear: in std_logic; cep, cet: in std_logic; qout: buffer integer range 0 to 7 ); end entity h145; architecture are_h145 of h145 is signal r: std_logic; begin process (clk) begin r <= cep and cet; if resetn = '0' then qout <= 0; elsif resetn = '1' and sclear = '1' then qout <=0; elsif resetn = '1' and sclear = '1' and r = '1' then qout <= qout+1 ; else qout <= qout; end if; end process; end architecture are_h145; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity h145_tb is end h145_tb; architecture are_h145_tb of h145_tb is component h145 port( resetn: in std_logic; clk: in std_logic; sclear: in std_logic; cep, cet: in std_logic; qout: buffer integer range 0 to 7 ); end component; signal resetn, clk,sclear,cet,cep: STD_LOGIC; signal qout:integer range 0 to 7; signal r:std_logic; begin gen_inst: h145 port map(resetn, clk,sclear,cep,cet ,qout); process begin r <= cep and cet; resetn <= '0'; wait for 10 ns; assert qout = 0 report "Test Case 1 Failed" severity error; sclear<= '1'; resetn<= '1'; wait for 10 ns; assert qout = 0 report "Test Case 1 Failed" severity error; sclear<= '0'; resetn<= '1';r<='1'; wait for 10 ns; assert qout =qout+1; report "Test Case 1 Failed" severity error; sclear<= '0'; resetn<= '1';r<='0'; wait for 10 ns; assert qout =qout report "Test Case 1 Failed" severity error; assert false report "End of test" severity note; wait; end process; end are_h145_tb; i accept the following errorError (10533): VHDL Wait Statement error at h145.vhd(52): Wait Statement must contain condition clause with UNTIL keyword Error (12153): Can't elaborate top-level user hierarchy what the probelm in dis program? Replies: Re: vhdl error Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed. Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Thank you and have a great day! Best Regards, Richard Tan Replies: Re: vhdl error Dropping a note to ask if my last reply was helpful to you? Do you need any further assistance from my side? Regards, Richard Tan Replies: Re: vhdl error Quartus software is not a simulator tool so you should Not compile testbench using it. Use the Questa Intel FPGA edition software or other third party simulator to compile the testbench. Quartus is primarily used for synthesizing, fitting, and generating programming files (like bitstreams) for FPGA devices. library ieee; use ieee.std_logic_1164.all; entity h145 is port ( resetn: in std_logic; clk: in std_logic; sclear: in std_logic; cep, cet: in std_logic; qout: buffer integer range 0 to 7 ); end entity h145; architecture are_h145 of h145 is signal r: std_logic; begin process (clk) begin r <= cep and cet; if resetn = '0' then qout <= 0; elsif resetn = '1' and sclear = '1' then qout <=0; elsif resetn = '1' and sclear = '1' and r = '1' then qout <= qout+1 ; else qout <= qout; end if; end process; end architecture are_h145; As what @roeekalinsky mentioned, the code above (entity h145) is synthesizable. The testbench code ( entity h145_tb) is not synthesizable and should Not be compiled using Quartus. Questa Intel FPGA Edition Simulation Flow Reference: Lite/Standard Edition: https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html Pro Edition: https://www.intel.com/content/www/us/en/docs/programmable/691278/current.html Regards, Richard Tan Replies: Re: vhdl error i want to write test bench for pogram h145 Replies: Re: vhdl error Looks like you're trying to synthesize your test bench, which makes no sense. Are you trying to synthesize or simulate? The test bench is for simulation only. Whereas for synthesis the top level should be entity h145 without the test bench.