Why does the Low Latency 100-Gbps Ethernet IP Core with CAUI-4 PCS and RS-FEC enabled generate periodic blocks of errors after 2 hours when implemented in the Intel® Arria® 10 GT device? - Why does the Low Latency 100-Gbps Ethernet IP Core with CAUI-4 PCS and RS-FEC enabled generate periodic blocks of errors after 2 hours when implemented in the Intel® Arria® 10 GT device? Description Due to a problem in the Intel® Quartus® Prime software versions 19.3 and earlier, the Low Latency 100-Gbps Ethernet IP Core with CAUI-4 PCS and RS-FEC enabled will generate periodic bursts of errors over time when implemented in the Intel® Arria® 10 GT device. Resolution To work around this issue, re-generate the IP core in the Intel® Quartus® Prime software 19.4 or later. Custom Fields values: ['novalue'] Troubleshooting 1409857123 False ['Low Latency 100G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.4 18.1 ['Arria® 10 GT FPGA'] ['novalue'] ['novalue'] ['novalue']