Why will packet loss be seen in Intel® Stratix® 10 L-Tile/H-Tile Transceivers 10G RX interface? - Why will packet loss be seen in Intel® Stratix® 10 L-Tile/H-Tile Transceivers 10G RX interface? Description Due to a problem in the Intel® Stratix® 10 L-Tile/H-Tile transceiver RX Core FIFO, packet loss will be observed in the RX interface if all the following conditions are met: Enhanced PCS transceiver RX Core FIFO is configured in 10GBASE-R mode Non-zero PPM between the TX link partner and the Intel Stratix 10 FPGA transceiver RX; and the Intel Stratix 10 FPGA RX CDR recovered clock is slower than the rx_coreclkin Resetting the transceiver PHY could trigger the problem Typical applications affected by this issue are as follows: 10GBASE-R, 10GBASE-R Low Latency or 10GBASE-R w/KR FEC presets in Native PHY IP 10GBASE-KR PHY IP 10GBASE-R Example Design of Low Latency Ethernet 10G MAC IP When the problem happens, the IDLE characters are incorrectly inserted between packet preambles. The corrupted packet header cannot be recognized at MAC layer resulting in packet loss. Resolution Use either of the following workarounds to avoid this problem: Use 0 PPM clocking between TX link partner and Intel® Stratix® 10 FPGA transceiver RX. Use the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP as an alternative, which implements similar RX Core FIFO functionality in core logic. This issue is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507015428 False ['10GBASE-R PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 17.0 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']