Why do I see unconstrained Input/Output Ports at EMIF pins when I compile the Agilex™ 7 FPGA M-Series EMIF IP? - Why do I see unconstrained Input/Output Ports at EMIF pins when I compile the Agilex™ 7 FPGA M-Series EMIF IP? Description You may see the unconstrained Input/Output Ports at EMIF pins when you compile the Agilex™ 7 FPGA M-Series EMIF IP. Resolution You can safely ignore these unconstrained warnings. The delay values for these pins are calibrated at run-time by the EMIF firmware, and those pins do not have values in the Timing Analysis. This problem is scheduled to be fixed in future releases of Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15014642896 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 23.3 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']