Using SystemVerilog with the Quartus® Prime Design Software - This instructor-led class is taught in a virtual classroom over a half-day of instruction. To perform the lab exercises, you will connect to a remote computer provided by the Altera® FPGA Training team, pre-configured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. Course Description SystemVerilog is a hardware description and verification language (HDVL) that is widely used in the electronic design automation (EDA) industry. It is a powerful and versatile language that combines the capabilities of hardware description languages (HDLs) such as VHDL and Verilog with the features of programming languages like C and C++. SystemVerilog is used to design, verify, and document electronic systems, including digital, analog, and mixed-signal systems. This training focuses on the SystemVerilog features for RTL design. You will learn efficient coding techniques for writing synthesizable SystemVerilog for Altera® FPGAs and SoCs. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions, including registers, memory, and arithmetic functions. Course Objectives At course completion, you will be able to: Understand the SystemVerilog data types and declarations Explore the SystemVerilog specialized procedural blocks Implement procedural statements, including SystemVerilog-enhanced case statements Implement state machines using SystemVerilog coding styles Take advantage of the enhanced port connections in SystemVerilog Understand the Compiler and state machine encoding settings in the Altera® Quartus® Prime Design Software Skills Required Background in digital logic design Completion of the "Advanced Verilog HDL techniques" course or some prior knowledge and use of Verilog hardware description language (HDL) Familiarity with the Quartus Prime Design Software If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_IHDL120. FPGA_IHDL120. <p>Verilog HDL Basics</p>