Why do I see bandwidth decrement in multi-channels DMA testing with the Multi Channel DMA Intel® FPGA IP for PCI Express? - Why do I see bandwidth decrement in multi-channels DMA testing with the Multi Channel DMA Intel® FPGA IP for PCI Express? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier, the bandwidth figure reported by the software driver shipped with the Multi Channel DMA for PCI Express Intel® FPGA IP Design Example may decrement in multi-channels testing. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 15010749146, 16012542562 False ['Wharf Rock Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 21.3 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']