Why do I see unexpected result when using Configuration Intercept Interface (CII) to access configuration space register with address greater than 8 bits on the P-Tile or F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express? - Why do I see unexpected result when using Configuration Intercept Interface (CII) to access configuration space register with address greater than 8 bits on the P-Tile or F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v22.1 and earlier version, configuration space register access using Configuration Intercept Interface (CII) with address greater than 8 bits may not work correctly when VIRTIO support is enabled. Configuration space register access where the lower 8 bits of the register address coincide with VIRTIO register will be recognized as VIRTIO register access regardless of the upper two address bits value. Resolution This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software v22.2. Custom Fields values: ['novalue'] Troubleshooting 15011281934 False ['Wharf Rock Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 22.1 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']