What is the size of the instruction cache on the HPS DMA Controller in Cyclone® V and Arria® V SoC devices? - What is the size of the instruction cache on the HPS DMA Controller in Cyclone® V and Arria® V SoC devices? Description The instruction cache size of the Arm DMA-330 IP on Cyclone® and Arria® V SoC series is 512 bytes. The cache line size is 8 words (4 bytes each), resulting in a line size of 32 bytes. There are a total of 16 cache lines, giving a total of 512 bytes. Resolution This information has been added in Cyclone V and Arria V HPS Technical Reference Manuals. Custom Fields values: ['novalue'] Troubleshooting 2205755526 False ['DMA'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']