AES-CCM: Authenticated Encrypt/Decrypt Engine - The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Intel® Arria® 10 GX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Intel® MAX® 10 FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Filters /Transforms Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless AES-CCM: Authenticated Encrypt/Decrypt Engine Key Features NIST-validated, realizes the AES Block Cipher, implemented according to NIST Special Publication 800-38D & employing Counter with CBC-MAC mode (CCM). Offering Brief Yes Yes No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Intel® Arria® 10 GX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Intel® MAX® 10 FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6vMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL, Encrypted VHDL, or FPGA netlist Ordering Information AES-CCM a1JUi0000049U6vMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-09-28T22:27:52.000+0000 The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Partner Solutions