UART receiver loopback characters VHDL - UART receiver loopback characters VHDL Greetings, I'm new to the world of FPGA's could anyone suggest me anything that helps me to learn implementing UART serial communication receiver loopback characters without state machines in VHDL Best regards, Tex Replies: Re: UART receiver loopback characters VHDL thanks for the help no more questions regarding this thread thank you regards Tex Replies: Re: UART receiver loopback characters VHDL Hi Tex, Do you need any further help on this thread? Thanks, Best Regards, Sheng Replies: Re: UART receiver loopback characters VHDL Hi Tex, Pins that should be assgined: I_clk I_reset I_txData (If you're getting the data externally from the board, then needed. Otherwise, not needed) O_tx, I_rx (Needed as to make loopback connection) O_rxData (If you're showing the received data externally to the board like LED or Monitor, then needed. Otherwise, not needed) For this I_txSig, you can comment out this input port and the rest in the code if you're not using it. For I_rxCont and I_clk_baud_count, you can declare them as signal instead of input port so that not need to make any pin assignment. For example like below: signal I_clk_baud_count : STD_LOGIC_VECTOR(15 downto 0) := X"01B2"; -- 115200bps @ 50Mhz Clk signal I_rxCont : STD_LOGIC := '1'; Pins that not needed to be assigned (monitor and debug purpose): If you want to assign, you can assign to for example like LED respectively. O_txRdy O_rxSig O_rxFrameError D_rxClk D_rxState D_txClk D_txState Thanks, Best Regards, Sheng Replies: Re: UART receiver loopback characters VHDL Thank you sheng this helped me alot.. for the link 1 when i try to assain pins there are showing more than 50 please tell me which pins should i assaign only 3 enough ??? regards, Tex Replies: Re: UART receiver loopback characters VHDL in test bench it is working Replies: Re: UART receiver loopback characters VHDL Hi Tex, You may check on this first example design link: https://github.com/Domipheus/UART https://domipheus.com/blog/a-uart-implementation-in-vhdl/ Make appropriate connection between O_tx and I_rx to form a loopback. The simulation result like below: This is second example design link (apparently state machine): https://nandland.com/project-7-uart-part-1-receive-data-from-computer/ https://www.edaplayground.com/x/7Em https://www.edaplayground.com/x/5vEh https://nandland.com/7-segment-display/ Make appropriate connection between o_TX_Serial and i_RX_Serial to form a loopback. The simulation result like below: Thanks, Best Regards, Sheng Replies: Re: UART receiver loopback characters VHDL Thanks for your valuable reply that's very help full tutorial for receiving I'm trying to achieve whatever the character i press in the keyboard it should receive in the serial monitor could you please help me Best regards, Tex Replies: Re: UART receiver loopback characters VHDL The concept of 'state machines' is not hard to learn, and in fact is indispensable when it comes to digital design in general. So I suggest you pursue learning state machine concepts, be it graphically or encoding the state machine into VHDL. It will make your life so much easier and more enjoyable when it comes to using FPGA technology. Here is a simple tutorial centered around using VHDL (I am a verilog guy myself): https://circuitdigest.com/microcontroller-projects/implementing-finite-state-machine-design-in-vhdl-using-modelsim There are lots of other tutorials on the web and youtube. Replies: Re: UART receiver loopback characters VHDL Thanks for your reply, I'm a student, I would like to learn UART with fpga in VHDL loopback what i mean is, if i enter in the keyboard any character it should display in the serial monitor i'm thinking state machines are tough to learn please help me with any kind of tutorials where i can learn it or any codes best regards, Tex Replies: Re: UART receiver loopback characters VHDL Hi, please elaborate your question. UART receiver implementation in VHDL is more or less clear, how is it specifically related to loopback? What's your problem with state machines?