Why does the simulation of the eSRAM Intel® FPGA IP targeting the Intel® Stratix® 10 using Mentor* ModelSim* show incorrect read data? - Why does the simulation of the eSRAM Intel® FPGA IP targeting the Intel® Stratix® 10 using Mentor* ModelSim* show incorrect read data?
Description When simulating the eSRAM Intel® FPGA IP targetting the Intel® Stratix® 10 devices with Mentor* ModelSim*, you may observe incorrect read data due to incorrect simulation options. Resolution To work around this problem, add the option below in the msim_setup.tcl file: set USER_DEFINED_VERILOG_COMPILE_OPTIONS "+define+ESRAM_SIM"
Custom Fields values:
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Troubleshooting
1508300397
False
['novalue']
['FPGA Dev Tools Quartus® Prime Software Pro']
novalue
20.3
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2022-09-21
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