Can I constrain the asynchronous resets of the LVDS SERDES FPGA IP as false paths? - Can I constrain the asynchronous resets of the LVDS SERDES FPGA IP as false paths? Description When closing timing, the LVDS SERDES IP's asynchronous resets can be constrained as false paths, following the guidelines of the Quartus® Prime Pro Edition User Guide: Design Recommendations 2.3.1.2. Using Asynchronous Resets. Resolution When adding the necessary constraints to your SDC file, follow the guidelines in the Quartus® Prime Pro Edition User Guide: Design Recommendations. Custom Fields values: ['novalue'] Troubleshooting 22020831082 False ['LVDS SERDES IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix No plan to fix ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2025-06-23