Why do I get a Fatal Error in Assembler when having ALTLVDS TX with a design? - Why do I get a Fatal Error in Assembler when having ALTLVDS TX with a design? Description You may see this error in the Quartus® Prime Software Standard version 17.0 or earlier. This error is due to either LVDS data output port “tx_out[*]” or external clock port “tx_outclock” of ALTLVDS TX IP is not assigned to LVDS I/O standard. Resolution To work around this problem, you should assign both the data output por t and external clock output to the LVDS I/O standard. Custom Fields values: ['novalue'] Troubleshooting FB: 436797; HSD: 2205833175 False ['LVDS SERDES IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 16.1 ['Arria® GX FPGA', 'Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® Bare Die', 'Stratix® FPGAs', 'Stratix® II FPGAs', 'Stratix® III FPGAs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']