Why is there an error when I run the UniPHY-based IP pin_assignments.tcl after Analysis & Synthesis is completed? - Why is there an error when I run the UniPHY-based IP pin_assignments.tcl after Analysis & Synthesis is completed? Description If you attempt to run the UniPHY-based <IP variation name>_pin_assignments.tcl after Analysis & Synthesis, you will get the following error: Error:"source "<path to file>/*_pin_assignments...." Resolution The workaround is to run a full compilation instead of Analysis & Synthesis and wait until the compilation fails during the Fitter. Then run the <IP variation name>_pin_assignments.tcl. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']