Why is the clock path information not listed in the Chip Planner when the register is inside the Partial Reconfiguration region? - Why is the clock path information not listed in the Chip Planner when the register is inside the Partial Reconfiguration region? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might not see the clock path information listed in the Chip Planner when the register is inside the Partial Reconfiguration (PR) region. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Troubleshooting 15011224955 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 21.4 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']