Why will the Altera 40G and 100G MACs produce the Error message,"tx padding state machine is corrupt" during simulation? - Why will the Altera 40G and 100G MACs produce the Error message,"tx padding state machine is corrupt" during simulation? Description The Altera® 40G and 100G MACs will display the error message,"tx padding state machine is corrupt" if the connected Avalon® interface was not driven as expected. The following rules must be followed: 1. Packets must start with an SOP which will also be the MSB of the data, and end with an EOP. No additional SOPs or EOPs are allowed within a packet. 2. Their must be a minimum of two clock cycles between packets. 3. tx_valid must remain high during packet transmission. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Stratix® IV GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']